CY7C199 Datasheet

• High speed
  • 10 ns
• Fast t_DOE
• CMOS for optimum speed/power
• Low active power
  • 467 mW (max, 12 ns "L" version)
• Low standby power
  • 0.275 mW (max, "L" version)
• 2V data retention ("L" version only)
• Easy memory expansion with /CE and /OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected

The CY7C199 is a high-performance CMOS static RAM organized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (/CE) and active LOW Output Enable (/OE) and three-state drivers. This device has an automatic power-down feature, reducing the power consumption by 81% when deselected. The CY7C199 is in the standard 300-mil-wide DIP, SOJ, and LCC packages.

An active LOW Write Enable signal (/WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O₀ through I/O₇) is written into the memory location addressed by the address present on the address pins (A₀ through A₁₄). Reading the device is accomplished by selecting the device and enabling the outputs, /CE and /OE active LOW, while /WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins.

The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and Write Enable (/WE) is HIGH. A die coat is used to improve alpha immunity.